
\section{Early design estimation for 3D ICs and 3D Cost
Model}\label{sec:cost-model}

To facilitate the design decision of using 3D integration from a
cost perspective, it is necessary to perform cost analysis at the
early design stage when detailed design information is not
available. The cost of an IC chip is closely related to the die
area. In 3D ICs, the Through-Silicon Vias (TSVs) may incur extra
area overhead. However, it is possible to use fewer number of metal
layers for routing in 3D ICs, which helps in cost reduction. In this
section, we describe how to estimate the die area, the metal layers
for feasible routing, and the impact of TSVs on die area, at the
very early design stage, when only limited design information (such
as the estimation of the gate counts in the design) is available.
%Such an early estimation will facilitate the 3D IC cost
%analysis. %discussed in Section~\ref{sec:costmodel}.

%deleted The Preliminary (Paul)
%\subsection{Rent's Rule}
%
%Our early design estimation is based on the well-known \emph{Rent's
%Rule}~\cite{route:rent}. Rent's Rule reveals the trend between the
%number of signal terminals and the number of internal gates. It is
%an empirical result based on the observations of existing designs,
%and can be expressed as:
%\begin{equation}
%T=kN_{g}^p
%\end{equation}
%where the parameters $k$ and $p$ are Rent's coefficient and
%exponent, $N_{g}$ is the gate counts, and $T$ is the number of
%signal terminals.
%
%Using Rent's Rule, it becomes possible to further estimate the
%average wire length~\cite{route:donath} and the wire length
%distribution~\cite{route:davis}. The average wire length can be
%given by:
%\begin{equation}
%\bar{R_{m}}=\frac{2}{9}\frac{1-4^{p-1}}{1-N_{g}^{p-1}}\left(7\frac{N_{g}^{p-0.5}-1}{4^{p-0.5}-1}-\frac{1-N_{g}^{p-1.5}}{1-4^{p-1.5}}\right)
%\label{equ:averagewire};
%\end{equation}
%When $p=0.5$, the expression can be calculated using
%\emph{L'Hospital Law}~\cite{route:donath}.
%%change when => When (Paul)
%
%According to Rent's rule, the wire length distribution function
%$i(l)$ has the forms as follows:
%
%Region I: $1 \le l \le \sqrt{N_{g}}$
%\begin{equation}
%i(l)=\frac{\alpha
%k}{2}\Gamma\left(\frac{l^3}{3}-2\sqrt{N_{g}}l^2+2N_{g}l\right)l^{2p-4}\nonumber
%\end{equation}
%
%Region II: $\sqrt{N_{g}} \le l < 2\sqrt{N_{g}}$
%\begin{equation}
%i(l)=\frac{\alpha k}{6}\Gamma\left(2\sqrt{N_{g}}-l\right)^3 l^{2p-4}
%\label{eqa:i2d}
%\end{equation}
%where $l$ is the interconnect length in units of gate pitches,
%$\alpha$ is the fraction of the on-chip terminals that are sink
%terminals and is related to the average fanout of a gate ($f.o.$) as
%follows:
%\begin{equation}
%\alpha=\frac{f.o.}{f.o.+1}
%\end{equation}
%and $\Gamma$ is given by
%\begin{equation}
%\Gamma=\frac{2N_{g}\left(1-N_{g}^{p-1}\right)}{\left(-N_{g}^{p}\frac{1+2p-2^{2p-1}}{p(2p-1)(p-1)(2p-3)}-\frac{1}{6p}+\frac{2\sqrt{N_{g}}}{2p-1}-\frac{N_{g}}{p-1}\right)}
%\end{equation}

\subsection{Die Area and Metal Layer Estimator}

At the early design stage, the die area can be estimated as a
function of the gate counts:
\begin{equation}
A_{die}=N_{g}A_{g} \label{equ:ori_area}
\end{equation}
where $N_{g}$ is the number of gates, and $A_{g}$ is an empirical
parameter that shows the proportional relationship between area and
gate counts. Based on empirical data from our industrial designs, in
this work, we assume that $A_{g}=3125\lambda^2$, in which $\lambda$
is half of the feature size for a specific technology node.
%delted "the" in "lambda is the half of the feature size" (Paul)


The number of required metal layers for routing depends on the
complexity of the interconnections. A simple metal layer estimation
can be derived from the average wire length~\cite{3dcost}:
\begin{equation}
n_{w}=\frac{f.o.\bar{R_{m}}p_{w}}{e_{w}}\sqrt{\frac{N_{g}}{A_{die}}}
\end{equation}
where $f.o.$ refers to the average gate fanout, $p_{w}$ to wire
pitch, $e_{w}$ to the utilization efficiency of metal layers,
$\bar{R_{m}}$ to the average wire length, which is formulated by
Equation~\ref{equ:averagewire}, and $n_{w}$ to the number of metal
layers.  Such simplified model is based on the assumptions that each
metal layer has the same utilization efficiency and the same wire
width~\cite{3dcost}. However, such assumptions may not be valid in
real design~\cite{route:kahng}. Moreover, the model in~\cite{3dcost}
does not include the impact of TSV area overhead,
which will be a considerable penalty when the complexity of 3D ICs increase. %fragment structre in "complexit of 3D ICs raises"...(Paul)

To improve the estimation of the number of metal layers needed for
feasible routing, we propose a new 3D routability model, which is
based on the wire length distribution rather than a simple
estimation of average wire length. The basic idea of this model is
explained as follows:

\begin{itemize}

%is i the metal layer (?) add that in describing variables; I did, make sure it is right(paul)
\item \textit{Estimate the available routing area of each metal layer with the expression:}
\begin{equation}
K_{i}=\frac{A_{die} \eta_{i}
-2A_{v}\left(N_{g}f.o.-I(l_{i})\right)}{w_{i}} \label{eqa:3D-K}
\end{equation}
where $i$ is the metal layer, $\eta_{i}$ is the layer's utilization
efficiency, $w_{i}$ is the layer's wire pitch, $A_{v}$ is the
blockage area of each via, and function $I(l)$ is the cumulative
integral of the wire length distribution function $i(l)$. %, which is
%expressed in Equation~\ref{eqa:i2d}.

\item \textit{Assume that shorter interconnects are routed on
lower metal layers. Starting from Metal 1, we route as many
interconnects as possible on the current metal layer until the
available routing area is used up.} The interconnects routed on each
metal layer can be express as:
%should chi be offset in the equation in the pdf? (Paul)
\begin{equation}
\chi L(l_{i})-\chi L(l_{i-1}) \le K_{i} \label{eqa:ml}
\end{equation}
where $\chi=4/(f.o.+3)$ is a factor accounting for the sharing of
wires between interconnects on the same
net\cite{route:davis}\cite{route:chong}. The function $L(l)$ is the
first-order moment of $i(l)$.

\item \textit{Repeat the same calculations for each metal layer in a bottom-up manner until all the interconnects are routed properly.}

\end{itemize}

By applying the estimation methodology introduced above, we can
predict the die area and the number of metal layers at the early
design stage where we only have the number of gates as the input.
Fig.~\ref{fig:est} shows an example which estimates the area and the
number of metal layers of 65nm designs with different scale of
gates.
%is scale of gates correct (Paul)

%why in Figure 2 does the # of gates decrease along the x-axis, usually the number of gates increase (Paul)
\begin{figure}[htbp]
\centering
%\vspace{-8pt}
\includegraphics[width=3.5in]{./figure/est.eps}
%\vspace{-10pt}
\caption{Early Design Estimation of Die Area and Metal Layer (65nm
process) (The estimation is well correlated with the
state-of-the-art microprocessor designs. For example, Sun SPARC
T2~\cite{SPARCT2} contains about $500M$ transistors (equivalent to
$125M$ gates), with an area of $342 mm^2$ and 11 metal layers)}
\label{fig:est} \vspace{-12pt}
\end{figure}

Fig.~\ref{fig:est} shows an important implication for 3D IC cost
reduction: \emph{When a large 2D chip is partitioned into multiple
smaller dies with 3D stacking, each smaller die requires fewer
number of metal layers to satisfy the interconnect routability
requirements}. Such metal layer reduction could offset the extra
cost resulting from 3D stacking.

\subsection{The Impact of TSVs}

The impact of Through-Silicon Vias (TSVs) used in 3D stacking on the
cost analysis are two folds: \squishlist \item In 3D ICs, some
global interconnects are now implemented by TSVs, going between
stacked ides. This could lead to the reduction of the total wire
length, and provides opportunities for metal layer reduction for
each smaller die; \item On the other hand, 3D stacking with
Through-Silicon Vias (TSVs) may increase the total die area, since
the silicon area where TSVs punch through may not be utilized for
building devices or 2D metal layer connections (Based on current
TSVs technologies, the diameter of TSVs ranges from $0.2\mu m$ to
$10\mu m$~\cite{3d:loh:micro2007}). \squishend

Consequently, it is important to estimate the number of TSVs and the
impact on the die area increase. The area overhead caused by TSVs
can be modeled as follows:
\begin{equation}
A_{3D}=A_{die}+N_{TSV/die}A_{TSV} \label{equ:tsv_impact}
\end{equation}
where $A_{die}$ is calculated by die area estimator, $N_{TSV/die}$
is the equivalent number of TSVs on each die, $A_{TSV}$ is the size
of TSVs, and $A_{3D}$ is the final 3D component die area.

%changed through silicon vias to TSVs(Paul)

%is the relation a derivation of Rent's rule:
%maybe; "a derivation of Rent's Rule describing the relationship between ..."

%To predict the number of required TSVs for a certain partition
%pattern, a derivation of Rent's Rule describing the relationship
%between the interconnections ($X$) and gates ($N_{g}$) can be
%used~\cite{route:donath}:
%\begin{equation}
%X=\alpha kN_{g}\left(1-N_{g}^{p-1}\right)
%\end{equation}
%
%\begin{figure}[htbp]
%\centering \vspace{-8pt}
%\includegraphics[width=3.4in]{./figure/tsv.eps}
%%\vspace{-10pt}
%\caption{The basic idea of how to estimate the number of TSVs}
%\label{fig:tsvest} \vspace{-12pt}
%\end{figure}
%
%As illustrated in Fig~\ref{fig:tsvest}, the number of TSVs can be
%estimated by:
%\begin{eqnarray}
%X_{TSV}=\alpha k_{1,2}(N_{1}+N_{2})\left(1-(N_{1}+N_{2})^{p_{1,2}-1}\right)\nonumber\\
%-\alpha k_{1}N_{1}\left(1-N_{1}^{p_{1}-1}\right)-\alpha
%k_{2}N_{2}\left(1-N_{2}^{p_{2}-1}\right) \label{equ:3d-idea}
%\end{eqnarray}
%
%%change 1,2 to subscripts Paul
%where $k_{1,2}$ and $p_{1,2}$ are the equivalent Rent's coefficient
%and exponent.


\subsection{3D Cost Model}

3D integration involves stacking multiple dies through traditional
fabrication processes. There are several different ways to stack
separate dies together~\cite{3D:DWM+05}, and the TSV-based approach
is the most promising approach. In addition to conventional 2D
processes, 3D integration needs extra fabrication steps such as
forming TSVs via laser drilling or etching, wafer thinning, and
wafer bonding. We model the cost brought by each step during the 3D
fabrication and the cost analysis can be divided into the die cost
model and the 3D bonding cost model as shown in
Fig.~\ref{fig:overview}.

\begin{figure}
[htbp] \centering
%\vspace{-8pt}
\includegraphics[width=3.4in]{./figure/overview_cost.eps}
%\vspace{-10pt}
\caption{The overview of the proposed 3D cost model}
\label{fig:overview}
%\vspace{-12pt}
\end{figure}

\begin{figure}
[htbp] \centering
%\vspace{-12pt}
\includegraphics[width=3.3in]{./figure/wafercost_example.eps}
%\vspace{-10pt}
\caption{A batch of data calculated by the wafer cost model. The
wafer cost varies from different processes, different number of
metal layers, different foundries, and some other factors.}
\label{fig:wafercost}
%\vspace{-20pt}
\end{figure}

%\squishlist
\begin{itemize}

\item \emph{Wafer Cost Model.} The key factor of the die cost
model is the die area. If we assume that the wafer cost, the wafer
yield, and the defect density are constant for a specific foundry
using a specific technology node, the impact of die areas can be
formulated by two expressions~\cite{ICbook} as following:
\begin{equation}
N_{die}=\frac{\pi \times(\phi_{wafer}/2)^2}{A_{die}}-\frac{\pi
\times \phi_{wafer}}{\sqrt{2\times A_{die}}}
\end{equation}
\begin{equation}
Y_{die}=Y_{wafer}\times\frac{\left(1-e^{-2A_{die}D_{0}}\right)}{2A_{die}D_{0}}
\label{equ:yield}
\end{equation}
where $N_{die}$ is the number of dies per wafer, $\phi_{wafer}$ is
the diameter of the wafer, $Y_{die}$ and $Y_{wafer}$ are the yields
of dies and wafers respectively, and $D_{0}$ is the defect density
of the wafer.

Our wafer cost model obtained from different foundries includes
material cost, labor cost, foundry margin, number of reticles, cost
per reticle, and other miscellaneous cost~\cite{costmodel}.
%The related
%industry data are all purchased from
%\emph{ICKnowledge.com}\cite{icknowledge}.
Fig.~\ref{fig:wafercost} shows the predicted wafer cost of $90nm$,
$65nm$, and $45nm$ processes, with $9$ or $10$ layers of metal, for
three different foundries, respectively.

\begin{figure}[htbp]
%\vspace{-8pt}
\centering
\includegraphics[width=2.5in]{./figure/3d_fab.eps}
%\vspace{-10pt}
\caption{Fabrication steps for 3D ICs: (a) TSVs are formed before
BEOL process, thus TSVs only punch through the silicon substrate but
not the metal layers; (b) TSVs are formed after BEOL process, thus
TSVs punch through not only the silicon substrate but the metal
layers as well.} \label{fig:3d}
%\vspace{-12pt}
\end{figure}

%changed step=>fabrication steps; added consist "of" (Paul)
%space before \emph{laser drilling (Paul)
%small number of tSVs => a small; large number => a large number (Paul) ?
%maybe itemize the TSV -first and TSV-later approach (Paul)
\item \emph{3D Bonding Cost.} The extra fabrication steps required by 3D
integrations consist of TSV forming, thinning, and bonding. There
are two ways to build 3D TSVs: \emph{laser drilling or etching}.
Laser drilling is only suitable for a small number of TSVs (hundreds
to thousands) while etching is suitable for a large number of TSVs.
TSV etching process is similar to building conventional vias between
metal layers, but as its name implies, TSV is ``through-silicon''.
There are two approaches for TSV etching: (1) \emph{TSV-first
approach:} TSVs can be formed during the 2D die fabrication process,
before the Back-End-of-Line (BEOL) processes. Such an approach is
called \emph{TSV-first} approach, and is shown in
Fig.~\ref{fig:3d}(a); (2) \emph{TSV-later approach:} TSVs can also
be formed after the completion of 2D fabrications, after the BEOL
processes. Such an approach is called \emph{TSV-later} approach, and
is shown in Fig.~\ref{fig:3d}(b). Our 3D bonding cost model is based
on the 3D process from our industry partners, with the assumption
that the yield of each 3D process step is $99\%$.

\item \emph{Overall 3D Cost Model.} In addition to the wafer cost
model and the bonding cost model, the entire 3D cost model also
depends on some design options, such as Die-to-Wafer/Wafer-to-Wafer
bonding, Face-to-Face/Face-to-Back bonding, and Known-Good-Die
cost~\cite{3d:cost}.

For D2W bonding, the bare chip cost before package is calculated by:
\begin{equation}
C_{D2W}=\frac{\sum_{i=1}^{N}
\left(C_{die_{i}+C_{KGDtest}}\right)/Y_{die_{i}} +
(N-1)C_{bonding}}{Y_{bonding}^{N-1}}
\end{equation}

For W2W bonding, the calculation becomes:
\begin{equation}
C_{W2W}=\frac{\sum_{i=1}^{N} C_{die_{i}} +
(N-1)C_{bonding}}{\left(\Pi_{i=1}^{N}
Y_{die_{i}}\right)Y_{bonding}^{N-1}}
\end{equation}

In order to support multiple-layer bonding, the default bonding mode
is Face-to-Back. If Face-to-Face mode is used, there is one more
component die that doesn't need the thinning process, and the
thinning cost of this die is subtracted from the total cost.
\end{itemize}
